ILP Bounds of SPEC Int95, SPECjvm98 and Mediabench Benchmarks

Wednesday, October 6, 1999 - 17:30
TH 331
William Hsu and Wanda Yee San Francisco State University
The instruction level parallelism (ILP) of an application is a measure of how many machine instructions can potentially be issued per cycle when the application is executed; it is a key determinant of execution time of an application on a multiple-issue architecture. We will describe simulation-based studies of various programs: selected benchmarks from the SPECint95 suite, Java applications from the SPECjvm98 suite, and multimedia applications from the Mediabench suite. The effect of hardware constraints such as lookahead window size, imperfect branch prediction using McFarling's gshare predictor and path history-based jump target prediction will be presented.

William Hsu is an Associate Professor of Computer Science at San Francisco State University. His current research interests are in high-performance processor and memory system architecture, performance evaluation, and interactive computer music. He received his PhD from the University of Illinois.

Wanda Yee received her M.S. Degree in Computer Science from San Francisco State University in 1999. She works for IBM in Austin, TX.