John Owens Stanford University
The Imagine Stream processor is a high-performance, power-efficient, programmable signal and image processor that achieves the performance density of special-purpose processors. This talk will highlight the key features of the Imagine Stream Architecture: large amounts of available arithmetic bandwidth, an area-efficient and power-efficient stream register organization, and a data bandwidth hierarchy which effectively manages data communication. By casting media applications into the stream programming model, they are able to take advantage of these architecture characteristics.
A prototype Imagine stream processor being designed at Stanford is targeted to operate at 500MHz with a die size of less than 1cm^2 when fabricated in a 0.15 micron process. With a peak performance of 20 GFLOPs on floating-point applications and over 40 GOPS on integer applications, a single Imagine processor sustains 19.2 GOPS on MPEG encoding. Other media applications perform similarly. This significantly outperforms modern high-performance processors and digital signal rocessors, while achieving power efficiencies competitive with special-purpose embedded processors.