Xtensa: A Configurable and Extensible Processor Core

Date: 
Wednesday, March 21, 2001 - 17:30
Location: 
TH 331
Presenter: 
Ricardo E. Gonzales Tensilica, Inc.
Abstract: 
The advent of configurable, extensible, and synthesizable processors has significantly changed the system design methodology. These configurable processors cores offer at least two unique advantages compared to hard-cores or pre-packaged components. First, they allow the system designer to define new instructions tailored to the application. Second, they are easier to integrate in a large ASIC. As recent EEMBC results show, designer-defined instructions can significantly increase application performance at a modest hardware cost. In this talk I will describe Xtensa, a configurable and extensible processor. I will begin by presenting an overview of the Xtensa; the Xtensa instruction set architecture (ISA), the current hardware implementation, and the configuration, extension and generation process. I will then describe how the system designer or application developer can customize and extend the base ISA using the Tensilica Instruction Extension (or TIE) language. Using DES as an example, I will show how to identify possible new instructions, how to evaluate the performance and cost of these instructions, and how to verify the correctness of the new instructions. I will show that adding application-specific instructions can significantly increase application performance for a modest hardware cost. Finally to demonstrate the power of TIE I will describe Vectra, a high-performance DSP instruction set developed entirely in TIE.
Bio: 

Dr. Ricardo E. Gonzalez is a member of the technical staff at Tensilica, Inc., where he is responsible for the development of high-performance, low power configurable processor cores. Before joining Tensilica Dr. Gonzalez was a member of the Micro-architectural Research Lab at Intel corporation. While at Intel he explored new architectural ideas for very high performance processors.

Dr. Gonzalez received his B.S., M.S., and Ph.D. from Stanford University in 1990, 1992, and 1997, respectively. His interests are in VLSI design, low power, high performance circuits, computer architecture, and CAD tools.