Managing Complexity in the Piranha Server-Class Processor Design

Date: 
Wednesday, October 16, 2002 - 17:30
Location: 
TH 331
Presenter: 
Rob Stets Compaq Western Research Labs
Abstract: 
High-end microprocessor designs have recently been incorporating increasingly advanced features, such as larger issue width and speculative out-of-order execution, which are targeted at further extracting instruction-level parallelism from programs. The added design complexity introduced by such mechanisms has led to an alarming increase in design cost and time-to-market for next generation designs. Although these mechanisms have improved performance of some applications, many important commercial workloads, such as online transaction processing, have not benefited significantly from them. In response to these trends, the Piranha project set out to address commercial workload performance requirements while managing overall project complexity. In this talk, we discuss the Piranha architecture and the project's novel design methodology, which together enabled the design to be brought to the point of a physical prototype by a team of less than 20 people working for little over a year.
Bio: 

Rob Stets has worked the Compaq, now the Hewlett-Packard, Western Research Laboratory for three years. The first two of the years were spent in the Piranha project. Rob obtained his Ph.D. degree from the University of Rochester's Computer Science Department, where he worked on issues in cluster computing. His general research interests are in the area of scalable server-based computing.