Rob Stets Compaq Western Research Labs
High-end microprocessor designs have recently been incorporating increasingly advanced features, such as larger issue width and speculative out-of-order execution, which are targeted at further extracting instruction-level parallelism from programs. The added design complexity introduced by such mechanisms has led to an alarming increase in design cost and time-to-market for next generation designs. Although these mechanisms have improved performance of some applications, many important commercial workloads, such as online transaction processing, have not benefited significantly from them.
In response to these trends, the Piranha project set out to address commercial workload performance requirements while managing overall project complexity. In this talk, we discuss the Piranha architecture and the project's novel design methodology, which together enabled the design to be brought to the point of a physical prototype by a team of less than 20 people working for little over a year.