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PERNET Colloquia
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Date and Time:
Wednesday, April 16, 2003
at 5:30PM
Location:
Thornton Hall 331
Presenter:
Michael Morrow
Intel
Subject:
Why is the Intel(r) XScale(tm) Core Scalar?
Abstract:

The Intel(r) XScale(tm) core was designed to deliver high performance while providing good efficiency (MIPS/Watt). We think a good way to meet these goals is to use a scalar microarchitecture, rather than superscalar. This talk will present some rationale behind such thinking.
Bio:

Mike Morrow has been a processor architect in the Intel(r) XScale(tm) Core design team since the first tape-out of this microarchitecture.

 
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